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XMEGA A [MANUAL]
8077I–AVR–11/2012
will change back to idle. If a collision is detected, the arbitration is assumed lost and the bus state becomes busy until a
STOP condition is detected. A repeated START condition will only change the bus state if arbitration is lost during the
issuing of the repeated START. Arbitration during repeated START can be lost only if the arbitration has been ongoing
since the first START condition. This happens if two masters send the exact same ADDRESS+DATA before one of the
masters issues a repeated START (Sr).
19.5
TWI Master Operation
The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate interrupts for master write
and master read. Interrupt flags can also be used for polled operation. There are dedicated status flags for indicating
ACK/NACK received, bus error, arbitration lost, clock hold, and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and
will in most cases require software interaction. Figure 19-12 shows the TWI master operation. The diamond shaped
symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL line.
Figure 19-12.TWI master operation.
The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command and
smart mode can be enabled to auto-trigger operations and reduce software complexity.
19.5.1 Transmitting Address Packets
After issuing a START condition, the master starts performing a bus transaction when the master address register is
written with the 7-bit slave address and direction bit. If the bus is busy, the TWI master will wait until the bus becomes idle
before issuing the START condition.
Depending on arbitration and the R/W direction bit, one of four distinct cases (M1 to M4) arises following the address
packet. The different cases must be handled in software.
IDLE
S
BUSY
P
Sr
P
M3
M2
M1
R
DATA
ADDRESS
W
A/A
DATA
Wait for
IDLE
APPLICATION
SW
Sr
P
M3
M2
BUSY
M4
A
SW
A/A
M4
A
IDLE
MASTER READ INTERRUPT + HOLD
MASTER WRITE INTERRUPT + HOLD
SW
BUSY
R/W
SW
Driver software
The master provides data
on the bus
Slave provides data on
the bus
A
R/W
BUSY
M4
Bus state
Mn
Diagram connections
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